Lecture 1 - Mathematical Logic - Session 1
Lecture 2 - Mathematical Logic - Session 2
Lecture 3 - Industry Perspectives on Compiler Design
Lecture 4 - Processor Datapath and Introduction to ILP Architecture - Session 1
Lecture 5 - Processor Datapath and Introduction to ILP Architecture - Session 2
Lecture 6 - Instruction Level Parallelism - Session 1
Lecture 7 - Multithreading and Multicores
Lecture 8 - Instruction Level Parallelism - Session 2
Lecture 9 - DRAM Memory Organization
Lecture 10 - Reactive Synthesis: A High-Level Introduction - Session 1
Lecture 11 - Reactive Synthesis: A High-Level Introduction - Session 2
Lecture 12 - Reactive Synthesis: A High-Level Introduction - Session 3
Lecture 13 - Reactive Synthesis: A High-Level Introduction - Session 4
Lecture 14 - Reduced Ordered Binary Dedision Diagrams and And-Inverter Graphs - Session 1
Lecture 15 - Reduced Ordered Binary Dedision Diagrams and And-Inverter Graphs - Session 2
Lecture 16 - Reduced Ordered Binary Dedision Diagrams and And-Inverter Graphs - Session 3
Lecture 17 - Runtime Environments - I
Lecture 18 - Runtime Environments - II
Lecture 19 - Hexagon DSPs in Snapdragon
Lecture 20 - Types and Program Analysis
Lecture 21 - Local and Global Optimizations
Lecture 22 - Introduction to Data-Flow and Control-Flow Analyses
Lecture 23 - Code Generation and Register Allocation
Lecture 24 - The Static Single Assignment Form and Application to Program Optimizations
Lecture 25 - Garbage Collection
Lecture 26 - Program Testing and Verification - Session 1
Lecture 27 - Program Testing and Verification - Session 2