NOC:Low Voltage CMOS Circuit Operation

Lecture 1 - Introduction and Motivation

Lecture 2 - Review of MOSFET operation - I

Lecture 3 - Review of MOSFET operation - II

Lecture 4 - Basic charge model - I

Lecture 5 - Basic charge model - II

Lecture 6 - Basic charge model - III

Lecture 7 - Basic charge model - IV

Lecture 8 - Basic charge model - V

Lecture 9 - Basic charge model - VI

Lecture 10 - Basic charge model - VII

Lecture 11 - Basic charge model - VIII

Lecture 12 - Basic charge model - IX

Lecture 13 - Basic charge model - X

Lecture 14 - Minimum energy point - I

Lecture 15 - Minimum energy point - II

Lecture 16 - Minimum energy point - III

Lecture 17 - Transistor sizing for combinational circuit - I

Lecture 18 - Transistor sizing for combinational circuit - II

Lecture 19 - Transistor sizing for asymmetric combinational circuits

Lecture 20 - Charging and discharging mechanism in NTV combinational gates

Lecture 21 - Effective current for NTV inverter

Lecture 22 - Effective current for NTV combinational gates - I

Lecture 23 - Effective current for NTV combinational gates - II

Lecture 24 - Effective current for NTV combinational gates - III

Lecture 25 - Combinational circuit design considering variations - I

Lecture 26 - Combinational circuit design considering variations - II

Lecture 27 - Buffer design considering INWE

Lecture 28 - Decoder design considering INWE

Lecture 29 - Flip-flop operation

Lecture 30 - Warning flip-flops design and operation

Lecture 31 - Single phase flip-flops design and operation

Lecture 32 - Consideration of radiation effects in NTV

Lecture 33 - Radiation-hardened NTV sequential circuit elements

Lecture 34 - Level shifters for multi-Vdd domains

Lecture 35 - Introduction to 6T SRAM

Lecture 36 - Stability and Reliability Issues in 6T SRAM

Lecture 37 - Read and Write-Assist Circuits in 6T SRAM

Lecture 38 - Physical Insights into Channel Charge Distribution

Lecture 39 - FinFET based Standard Cell Design

Lecture 40 - Example problems