NOC:Optimization Techniques for Digital VLSI Design

Lecture 1 - Introduction to Digital VLSI Design Flow

Lecture 2 - High-level Synthesis (HLS) flow with an example

Lecture 3 - Automation of High-level Synthesis Steps

Lecture 4 - Impact of Coding Style on HLS Results

Lecture 5 - Impact of Compiler Optimizations on HLS Results

Lecture 6 - RTL Optimizations for Timing

Lecture 7 - Retiming

Lecture 8 - RTL Optimizations for Area

Lecture 9 - RTL Optimizations for Power

Lecture 10 - High Level Synthesis: Introduction to Logic Synthesis

Lecture 11 - Overview of FPGA Technology Mapping

Lecture 12 - Introduction to Physical Synthesis

Lecture 13 - Introduction to Digital VLSI Testing - I

Lecture 14 - Introduction to Digital VLSI Testing - II

Lecture 15 - Optimization Techniques for ATPG - Part I

Lecture 16 - Optimization Techniques for ATPG - Part II

Lecture 17 - Optimization Techniques for Design for Testability

Lecture 18 - High-level fault modeling and RTL level Testing

Lecture 19 - LTL/CTL based Verification

Lecture 20 - Verification of Large Scale Systems

Lecture 21 - BDD based verification

Lecture 22 - Verification: ADD based verification, HDD based verification

Lecture 23 - Verification: Symbolic Model Checking

Lecture 24 - Verification: Bounded Model Checking